TREE NEWS update: Huawei Semiconductor EDA chief scientist Huang Yu said on Oct. 15 at the 2026 Wanxin Expo that Huawei’s “Tao Law” spans four layers: the device layer, optimizing transistor structure and interconnection to compress device time constants; the link layer, which he called Huawei’s biggest innovation; the chip layer, using hardware-software co-design for new architectures; and the system layer, covering super nodes and cabinet interconnection requiring better communication protocols and faster speeds.
Huawei EDA Chief Scientist Huang Yu Outlines Four-Layer ‘Tao Law’ at 2026 Wanxin Expo
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AI take
Framing chip progress as a four-layer stack rather than a single process-node race is the notable move here: it puts Huawei's emphasis on the link layer and on system-level interconnect, where domestic constraints bite less than at the leading edge. The audience is anyone tracking China's semiconductor self-sufficiency path, since EDA sits at the design bottleneck. Whether these layers translate into measurable design wins, and whether the link layer holds up as the claimed differentiator, is the open question.
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